RISC-V Simulator
A simulator for running RISC-V machine code.
Members: Arnav Kharbanda*, Yashasav Prajapati*, Gopal Bansal*. Shobhit Juglan*
Github: Github Website: Website
RISC-V Simulator
I developed a RISC-V simulator using C and Python to run RISC-V machine code. The simulator includes the following features:
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Pipelining: I implemented pipelining to simulate different stages of instruction execution, which helps speed up the processing of instructions.
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Data Forwarding: To handle data dependencies more efficiently, I added data forwarding. This feature allows the results from earlier pipeline stages to be used directly in later stages, improving performance.
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Cache Memory: The simulator also supports cache memory, which speeds up memory access by storing frequently used data in faster memory, reducing delays.
Conclusion:
Building this RISC-V simulator was a fun and rewarding project. It gave me a deeper understanding of how processors handle instructions and memory. With features like pipelining, data forwarding, and cache memory, the simulator efficiently runs RISC-V machine code and can be used for both learning and performance analysis.
